Sony patents stacked camera chip design with improved electrical isolation
Sony describes a camera sensor made of two stacked semiconductor layers, with the top layer holding the circuitry that processes image data. The design features specific insulating barriers around the connection points between the layers to prevent electrical interference.
In the filing’s own words
A solid-state imaging device includes a first semiconductor layer, a second semiconductor layer, and an external terminal. The first semiconductor layer has a pixel region in which a plurality of pixels is arranged, and a peripheral region provided around the pixel region. The second semiconductor layer is stacked on the first semiconductor layer, and is provided with a pixel circuit coupled to the pixels. The external terminal is provided in an opening that communicates with the second semiconductor layer from the peripheral region in the first semiconductor layer. A first isolator is provided in the first semiconductor layer within the peripheral region, and surrounds at least a portion of an outer periphery of the opening. A second isolator is provided in the second semiconductor layer within a region corresponding to the peripheral region, and surrounds at least a portion of the outer periphery of the opening.
What exactly they claim (claim 1)
1. A solid-state imaging device, comprising: a first semiconductor layer having a pixel region and a peripheral region, the pixel region in which a plurality of pixels is arranged, and the peripheral region provided around the pixel region; a second semiconductor layer stacked on the first semiconductor layer on side opposite to light incident side of the pixels, the second semiconductor layer being provided with a pixel circuit coupled to the pixels; an external terminal provided in an opening that communicates with the second semiconductor layer from the peripheral region in the first semiconductor layer; a first isolator provided in the first semiconductor layer within the peripheral region, the first isolator surrounding at least a portion of an outer periphery of the opening; and a second isolator provided in the second semiconductor layer within a region corresponding to the peripheral region, the second isolator surrounding at least a portion of the outer periphery of the opening.
Facts
- Company
- Sony (SONY SEMICONDUCTOR SOLUTIONS CORPORATION)
- Official title
- Solid-state imaging device and method of manufacturing solid-state imaging device
- Patent number
- US12765082B2
- Application number
- 18550732
- Filed
- Jan 11, 2022
- Granted
- Oct 13, 2026
- Inventors
- 4
- Claims
- 18
Classified under
H10F 39/026 Electricity & electronicsH10F 39/184 Electricity & electronicsH10F 39/807 Electricity & electronicsH10F 39/809 Electricity & electronicsH10F 39/811 Electricity & electronicsH10W 42/121 Electricity & electronicsMore from Sony in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.