Nvidia patents circuit board design that skips layers to improve signal quality
Nvidia has been granted a patent for a specific layout of holes, or vias, in printed circuit boards. The design uses 'buried skip vias' that connect non-adjacent layers inside the board, bypassing middle layers to create shorter paths for electrical signals and power. This arrangement is intended to reduce interference and maintain signal integrity as circuit boards become more complex.
In the filing’s own words
A printed circuit board (PCB) includes an exterior section having a first set of layers including an outermost conductive layer. The PB further includes an interior section, adjacent to the exterior section, having a second set of layers including a first conductive layer corresponding to a first end of the interior section, a second conductive layer corresponding to a second end of the interior section opposite the first end, and a third conductive layer disposed between the first conductive layer and the second conductive layer. The exterior section further includes a set of vias extending from an outermost conductive layer to the first conductive layer. The interior section further includes a buried skip via extending from the first conductive layer to the third conductive layer.
What exactly they claim (claim 1)
1. A device comprising: a first exterior section of a printed circuit board (PCB), the first exterior section of the PCB comprising at least three conductive layers including a first outermost conductive layer of the PCB; a second exterior section of the PCB, the second exterior section of the PCB comprising at least three conductive layers including a second outermost conductive layer of the PCB; and an interior section of the PCB, disposed between the first exterior section of the PCB and the second exterior section of the PCB, comprising a first interior conductive layer corresponding to a first end of the interior section, a second interior conductive layer corresponding to a second end of the interior section opposite the first end, a third interior conductive layer disposed between the first interior conductive layer and the second interior conductive layer, a fourth interior conductive layer disposed between the first interior conductive layer and the second interior conductive layer, a fifth interior conductive layer disposed between the first interior conductive layer and the third interior conductive layer, and a sixth interior conductive layer disposed between the second interior conductive layer and the fourth interior conductive layer; wherein the first exterior section of the PCB further comprises a first set of vias comprising at least three vertically arranged vias, the first set of vias extending from the first outermost conductive layer to the first interior conductive layer; wherein the second exterior section of the PCB further comprises a second set of vias comprising at least three vertically arranged vias, the second set of vias extending from the second outermost conductive layer to the second interior conductive layer; and wherein the interior section of the PCB further comprises: buried skip vias each corresponding to a via having ends connected to respective interior conductive layers of the interior section of the PCB that are separated by at least one layer of the interior section of the PCB, wherein the buried skip vias comprise a first buried skip via extending from the first interior conductive layer to the third interior conductive layer and bypassing the fifth interior conductive layer, and a second buried skip via extending from the second interior conductive layer to the fourth interior conductive layer and bypassing the sixth interior conductive layer; an additional buried via that spans the interior section by extending from the first interior conductive layer to the second interior conductive layer; a first additional via directly underneath the first set of vias and having an end connected to the fifth interior conductive layer; and a second additional via directly underneath the second set of vias and having an end connected to the sixth interior conductive layer.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- Buried skip vias for improved signal and power integrity
- Patent number
- US12757327B2
- Application number
- 18197146
- Filed
- May 15, 2023
- Granted
- Oct 6, 2026
- Inventors
- 4
- Claims
- 12
Classified under
H05K 1/115 Electricity & electronicsH05K 3/4644 Electricity & electronicsH05K 1/0251 Electricity & electronicsH05K 2201/09509 Electricity & electronicsH05K 2201/09536 Electricity & electronicsH05K 2201/096 Electricity & electronicsMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.