Sony patents video signal stabilizer for unstable network connections
Sony describes a data processing device that recovers video signals from unstable transmission paths like networks. When signal timing errors, known as jitter, are detected, the device locks the clock signal and sends out dummy data to keep the connection stable for the next device.
In the filing’s own words
The CDR in a reception device (sink device) at a subsequent stage can be prevented from being unlocked even when jitter-fluctuation occurs due to transmission via an unstable transmission path such as a network. The clock data recovery unit extracts a clock and data on the basis of the baseband video data of a first format corresponding to a predetermined transmission path input from the predetermined transmission path. The extracted data is processed by the processing unit on the basis of the extracted clock. In this case, in a case where the occurrence of the jitter-fluctuation is detected, dummy data capable of clock extraction at the subsequent stage is output. For example, the processing unit outputs baseband video data in a second format, and the baseband video data in the second format is baseband video data corresponding to a predetermined wired interface.
What exactly they claim (claim 1)
1. A data processing device, comprising: a clock data recovery unit configured to: receive baseband video data from a specific transmission path; and extract, based on the received baseband video data, a clock and data, wherein the received baseband video data is in a first format corresponding to the specific transmission path, and the clock data recovery unit includes: a phase detector configured to: detect a phase difference between the received baseband video data in the first format and the clock; and output an analog amount corresponding to the phase difference; a low-pass filter configured to smooth an output of the phase detector, wherein the output of the phase detector includes the analog amount; and a voltage-controlled oscillator configured to output the clock wherein an output of the low-pass filter is input to a control voltage terminal of the voltage-controlled oscillator, and in a case where an occurrence of a jitter-fluctuation is detected, a voltage input to the control voltage terminal is fixed to the output of the low-pass filter immediately after the occurrence of the jitter-fluctuation; and the voltage-controlled oscillator is further configured to continue to output the clock in a state immediately after the occurrence of the jitter-fluctuation; and a processing unit configured to: process, based on the clock, the extracted data; and in the case where the occurrence of the jitter-fluctuation is detected, output dummy data that is capable of clock extraction at a subsequent stage.
Facts
- Company
- Sony (SONY GROUP CORPORATION)
- Official title
- Data processing device and data processing method
- Patent number
- US12750561B2
- Application number
- 18864552
- Filed
- May 9, 2023
- Granted
- Sep 29, 2026
- Inventors
- 5
- Claims
- 17
Classified under
H04N 21/64792 Electricity & electronicsH04B 10/40 Electricity & electronicsH04L 7/033 Electricity & electronicsMore from Sony in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.