Amazon patents method to shrink chip design files for faster checks
Amazon describes a software method that trims large computer files used to design computer chips. It keeps only the connection points between parts, removing unnecessary data to make the files smaller and easier to process.
In the filing’s own words
Systems and methods parse integrated circuit (IC) design files to identify boundary conditions between components. The boundary conditions may correspond to connections between different components, at various levels of the IC, that may create antennas during one or more manufacturing processes. The identified boundary conditions may be extracted from the design files to generate lighter weight design files that eliminate parameters that are not associated with the boundary conditions. Design files for each component within a system may be parsed and checked for boundary conditions prior to delivery and integration to a top level design file. Thereafter, the top level may be executed with a run-set, such as to perform an antenna check.
What exactly they claim (claim 1)
1. A computer-implemented method, comprising: receiving a design file for a component of an integrated circuit (IC), the design file having a first quantity of data content; determining, based on one or more indicators associated with the design file, one or more boundary conditions corresponding to connections between the component and one or more additional components of the IC; extracting, from the design file, the one or more boundary conditions; generating, using the extracted one or more boundary conditions, a skin design for the component representing the one or more boundary conditions of the component, the skin design having a second file size with less data content than a first file size; generating, using at least the skin design, a top level skin design; and executing, on the top level skin design, an antenna check.
Facts
- Company
- Amazon (Amazon Technologies, Inc.)
- Official title
- Reducing component database size for reduced run-set evaluation
- Patent number
- US12748907B1
- Application number
- 18083115
- Filed
- Dec 16, 2022
- Granted
- Sep 29, 2026
- Inventors
- 2
- Claims
- 20
Classified under
G06F 30/398 Physics & computingG06F 30/392 Physics & computingMore from Amazon in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.