Nvidia patents chip that splits one core into two on the fly
This patent describes a method for dynamically reconfiguring a single processor core into two smaller, independent cores. When a command is issued, the existing processing pipeline and hardware resources are partitioned so that two different tasks can run in parallel without sharing stages.
In the filing’s own words
A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. In response to a command to operate the IC with multiple cores, the first pipeline is flushed. The first core is partitioned to obtain a second core and a third core. The first pipeline is partitioned to obtain a second pipeline and a third pipeline. The first set of hardware structures is partitioned to obtain a second set of hardware structures and a third set of hardware structures. The first thread is executed on the second pipeline of the second core of the IC, the second core including the second set of hardware structures. A second thread is executed on the third pipeline of the third core of the IC, the third core including the third set of hardware structures.
What exactly they claim (claim 1)
1. A method for operating an integrated circuit (IC), the method comprising: executing a first thread on a first pipeline of a first core of the IC, the first core comprising a first set of hardware structures, and the first pipeline comprising a set of sequential processing stages through which a sequence of instructions of the first thread progresses to complete execution; and in response to a command to operate the IC with a plurality of cores: partitioning the first core to obtain a second core and a third core such that the second core and the third core each independently execute a respective different sequence of instructions in parallel, wherein partitioning the first core comprises partitioning the first pipeline to obtain a second pipeline and a third pipeline such that each of the second pipeline and the third pipeline is an independent, statically partitioned pipeline of sequential processing stages without sharing pipeline stages with the other pipeline, through which the respective different sequence of instructions of the respective thread progresses to complete execution, and partitioning the first set of hardware structures to obtain a second set of hardware structures and a third set of hardware structures such that the second core has exclusive access to the second set of hardware structures and the third core has exclusive access to the third set of hardware structures executing the first thread on the second pipeline of the second core of the IC, the second core comprising the second set of hardware structures; and executing a second thread on the third pipeline of the third core of the IC, the third core comprising the third set of hardware structures.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- Dynamic reconfiguration of a unified core processor to a multi-core processor
- Patent number
- US12743395B2
- Application number
- 18813666
- Filed
- Aug 23, 2024
- Granted
- Sep 22, 2026
- Inventors
- 10
- Claims
- 20
Classified under
G06F 15/7878 Physics & computingG06F 9/30079 Physics & computingG06F 9/3867 Physics & computingG06F 9/4812 Physics & computingG06F 15/7867 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.