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Amazon patents memory design that splits data across channels

This patent describes a method for writing data to computer memory by splitting a single piece of data across two separate memory sub-channels within a module. A reliability control circuit handles the write request, sending half the data to one sub-channel and the other half to a second sub-channel to improve overall reliability.

Why it mattersThis is a low-level hardware improvement that helps ensure data is stored correctly in servers and computers, though it is unlikely to be visible to everyday users.

In the filing’s own words

Techniques to improve the reliability of volatile memory may include receiving a write request to store a data chunk in a volatile memory implemented using a memory module that contains a plurality of memory sub-channels. In response to the write request, a first write access is performed to write at least a first portion of the data chunk into a first memory sub-channel of the memory module, and a second write access is performed to write at least a second portion of the data chunk into a second memory sub-channel of the memory module.

What exactly they claim (claim 1)

1. A computing system comprising: a host processor; a reliability control circuit; and a volatile memory implemented using a plurality of memory modules, each of the memory modules having a plurality of memory sub-channels, wherein each memory sub-channel includes a plurality of memory designated for storing data and at least one memory die designated for storing error correction code information for the data stored in the plurality of memory dies, wherein the reliability control circuit is operable to: receive a write request from the host processor to store a cache line at a target address in the volatile memory; and in response to the write request, perform a first write burst chop access to write a first half of the cache line into a first set of memory dies of a first memory sub-channel of a memory module; and perform a second write burst chop access to write a second half of the cache line into a second set of memory dies of a second memory sub-channel of the memory module.

Facts

Company
Amazon (Amazon Technologies, Inc.)
Official title
Memory sub-channel reliability
Patent number
US12737126B1
Application number
18902239
Filed
Sep 30, 2024
Granted
Sep 15, 2026
Inventors
3
Claims
19

Classified under

G06F 3/0619 Physics & computingG06F 3/0659 Physics & computingG06F 3/0673 Physics & computingG06F 11/1044 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.