/Patent Tracker
SonyGranted patentChips & hardwareInterest 3/10

Sony patents digital circuit design for precise clock synchronization

Sony has secured a patent for an all-digital phase-locked loop circuit that uses two parallel time-to-digital converters to measure phase differences. One converter provides a coarse measurement, while the other offers finer resolution and can be turned off when not needed to save power. The circuit outputs a signal to synchronize the reference clock with the digital components of the chip.

Why it mattersThis design improves the accuracy and efficiency of internal timing signals within computer chips, which is a standard engineering improvement for hardware performance.

In the filing’s own words

All digital phase-locked loop circuits are disclosed. In one example, an all digital phase-locked loop circuit includes a first time-to-digital converter that performs phase difference detection at a first resolution, and a second time-to-digital converter that performs phase difference detection at a second resolution finer than the first resolution and that is arranged in parallel with the first time-to-digital converter. The second time-to-digital converter is configured to allow it to be disabled, and the first time-to-digital converter outputs a clock synchronization selection signal used for synchronizing a reference clock signal to a clock synchronization unit that generates a clock signal of a digital part.

What exactly they claim (claim 1)

1. An all digital phase-locked loop circuit comprising: a first time-to-digital converter that performs phase difference detection at a first resolution; and a second time-to-digital converter that performs phase difference detection at a second resolution finer than the first resolution and that is arranged in parallel with the first time-to-digital converter, wherein the second time-to-digital converter is configured to allow being disabled, and the first time-to-digital converter outputs a clock synchronization selection signal used for synchronizing a reference clock signal to a clock synchronization circuit that generates a clock signal of a digital part.

Facts

Company
Sony (Sony Semiconductor Solutions Corporation)
Official title
All digital phase-locked loop circuit
Patent number
US12732197B2
Application number
18841566
Filed
Mar 20, 2023
Granted
Sep 8, 2026
Inventors
4
Claims
11

Classified under

H03L 7/087 Electricity & electronicsH03L 7/0802 Electricity & electronicsH03L 7/085 Electricity & electronicsH03L 7/0991 Electricity & electronicsH03L 7/197 Electricity & electronicsH03L 2207/50 Electricity & electronics

More from Sony in Chips & hardware

Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.