Nvidia patents chip design that adds numbers using logs to save power
Nvidia describes a hardware design for processing neural networks that performs math using logarithmic numbers instead of standard formats. The system breaks down these numbers into parts, sorts them, and uses a special accumulator to add them up more efficiently than converting them to regular integers first.
In the filing’s own words
Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.
What exactly they claim (claim 1)
1. A processing element, comprising: a set of M vector inference engines, each vector inference engine comprising: a vector adder configured to compute product values by summing each weight in a set of weights with each activation in a set of activations, wherein the weights and the activations are represented in logarithmic form, each product value including a quotient component and a remainder component; N arrays of asynchronous accumulators, wherein, within each one of the N arrays: each asynchronous accumulator corresponds to a different possible value of the remainder component and is configured to increment or decrement a single bit of a partial sum based on the quotient component; and a scale unit coupled to each asynchronous accumulator multiplies the partial sum by the value of the remainder component corresponding to the asynchronous accumulator to produce a scaled partial sum; and an addition unit adds the scaled partial sums to produce a sum of the product values.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- Asynchronous accumulator using logarithmic-based arithmetic
- Patent number
- US12731019B2
- Application number
- 18674632
- Filed
- May 24, 2024
- Granted
- Sep 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G06N 3/063 Physics & computingG06F 7/575 Physics & computingG06F 17/16 Physics & computingG06N 3/02 Physics & computingG06F 7/5443 Physics & computingG06N 3/045 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.