Nvidia patents circuit to detect clock signal timing errors
Nvidia describes a hardware circuit that monitors the timing of a chip's internal clock signal. It uses pulse generators and counters to measure the duration of each clock phase and flags an error if the timing becomes too slow or too fast.
In the filing’s own words
Circuitry and a method of operating a clock monitoring circuit for monitoring a clock signal is disclosed. The method comprises generating a train of pulses corresponding to a duration of respective phases of a clock signal, counting a number of pulses in respective generated pulse trains, determining (using the number of pulses) when durations of subsequent phases of the clock signal lengthen, determining (using the number of pulses) when durations of the subsequent phases of the clock signal shorten, and providing a clock abnormality detect (CAD) signal when the clock signal either lengthens or shortens. The number of pulses in each respective pulse train is indicative of the duration of the respective phases of the clock signal.
What exactly they claim (claim 1)
1. A clock monitoring circuit for monitoring a clock signal, comprising: two ring pulse generators, each configured to generate a train of pulses corresponding to a duration of respective phases of the clock signal; two n-bit counters, each connected to a respective one of the two ring pulse generators, configured to count a number of pulses in respective pulse trains generated by the two ring pulse generators, wherein a count of the number of pulses in each respective pulse train is indicative of a duration of the respective phases of the clock signal; a clock slow detection (CSD) circuit configured to assert a CSD signal when durations of subsequent phases of the clock signal lengthen; a clock fast detection (CFD) circuit configured to assert a CFD signal when durations of subsequent phases of the clock signal shorten; and a logic circuit configured to provide a clock abnormality detect (CAD) signal when either the CSD signal or the CFD signal is asserted.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- Low power and area clock monitoring circuit using ring delay arrangement
- Patent number
- US12730148B2
- Application number
- 18295493
- Filed
- Apr 4, 2023
- Granted
- Sep 8, 2026
- Inventors
- 2
- Claims
- 20
Classified under
G01R 31/31727 Physics & computingG05B 19/4155 Physics & computingG06F 1/14 Physics & computingG05B 2219/32388 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.