Apple patents memory system handling different page sizes in processors
Apple describes a design for a translation lookaside buffer (TLB), a fast memory component that helps processors find where data is stored. The system uses separate storage areas to handle virtual addresses for pages of different sizes, allowing the processor to quickly retrieve the correct physical memory location.
In the filing’s own words
Disclosed herein are systems and methods for indexing multiple page sizes in a set associative TLB. For example, a TLB includes tag memory devices configured to store virtual addresses for pages of a first size and a second size, respectively, and a data memory device configured to store physical addresses of the pages of both sizes. The TLB receives a translation request to translate a virtual address to a physical address. The TLB provides, based on the request, lookup requests comprising portions of the virtual address to the tag memory devices. The TLB determines that one of the portions of the virtual address is stored in one of the tag memory devices. The TLB obtains the physical address of the page from the data memory device based on a determination that that one of the portions of the virtual address is stored in one of the tag memory devices.
What exactly they claim (claim 1)
1. A system, comprising: at least one processor configured to provide a translation request to translate a virtual address of a page to a physical address of the page; and a translation lookaside buffer comprising: a first tag memory device configured to store first virtual addresses of first pages of a first size; a second tag memory device configured to store second virtual addresses of second pages of a second size; and a data memory device configured to store physical addresses of the first pages and the second pages, wherein the translation lookaside buffer is configured to: provide, based on the translation request, a first lookup request comprising a first portion of the virtual address to the first tag memory device and a second lookup request comprising a second portion of the virtual address to the second tag memory device; determine that the first portion of the virtual address is stored in the first tag memory device or the second portion of the virtual address is stored in the second tag memory device based on provision of the first lookup request and the second lookup request; obtain the physical address of the page from the data memory device based on a determination that the first portion of the virtual address is stored in the first tag memory device or the second portion of the virtual address is stored in the second tag memory device; and provide the physical address to the at least one processor for retrieval of the page based on the physical address.
Facts
- Company
- Apple (Apple Inc.)
- Official title
- OPTIMAL SET INDEXING OF MULTIPLE PAGE SIZES IN A SET ASSOCIATIVE TRANSLATION LOOKASIDE BUFFER
- Publication number
- US20260329766A1
- Application number
- 19181438
- Filed
- Apr 17, 2025
- Published
- Oct 22, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G06F 12/0292 Physics & computingG06F 2212/1028 Physics & computingMore from Apple in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.