Apple patents method to clear outdated memory maps in chips
Apple describes a system where a processor sends a specific signal through the chip's internal network to tell other parts to delete old address translations. This ensures that when the computer's memory map changes, all components immediately use the correct, up-to-date locations for data.
In the filing’s own words
Techniques are disclosed relating to invalidating cached address translations. A system includes a processor complex, subsystems, and a communication fabric. The subsystems may include respective sets of memory management circuits that cache virtual-to-physical address translations of a set of page tables, and the processor complex includes one or more processor cores. Invalidation management circuitry of the communication fabric may receive, from a processor core of the processor complex, a write request having a translation invalidation payload. The invalidation management circuitry converts the write request into a translation invalidation request to invalidate one or more address translations and forwards the translation invalidation request on the communication fabric to one or more of the subsystems. The invalidation management circuitry receives, from those subsystems, translation invalidation responses indicating that the translation invalidation request has been completed. The invalidation management circuitry issues, to the processor core, a write response to the write request.
What exactly they claim (claim 1)
1. A system, comprising: a processor complex that includes one or more processor cores; a plurality of subsystems, wherein a given subsystem of the plurality of subsystems includes a respective set of memory management circuits, and wherein a given memory management circuit of the respective set of memory management circuits is configured to cache one or more of a plurality of virtual-to-physical address translations of a set of page tables; and a communication fabric coupled to the one or more processor cores and the plurality of subsystems and is configured to facilitate communication between the one or more processor cores and the plurality of subsystems; wherein a particular processor core of the one or more processor cores is further configured to: perform an update on the set of page tables; and issue, to the communication fabric, a write request that includes a translation invalidation payload associated with the update; and wherein the communication fabric includes a first fabric circuit that is configured to: receive the write request; convert the write request into a translation invalidation request to invalidate, based on the translation invalidation payload, one or more virtual-to-physical address translations, wherein the translation invalidation request targets one or more subsystems of the plurality of subsystems; and forward the translation invalidation request on the communication fabric.
Facts
- Company
- Apple (Apple Inc.)
- Official title
- Mechanisms for Invalidating Address Translations Cached in Memory Management Circuits
- Publication number
- US20260319961A1
- Application number
- 19175625
- Filed
- Apr 10, 2025
- Published
- Oct 15, 2026
- Inventors
- 6
- Claims
- 20
Classified under
G06F 12/0891 Physics & computingMore from Apple in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.