Apple patents memory trick to reduce errors in fast data reads
Apple describes a method for reading data from nonvolatile memory by adjusting the voltage on nearby electrical lines to reduce interference. The system reads the same data multiple times under different voltage conditions and uses logic to determine the correct bits and how confident it is in each one.
In the filing’s own words
A storage system includes circuitry and memory cells that are coupled to multiple WLs and to multiple BLs. The circuitry includes combinational logic, and is configured to: set a read voltage to a target WL, and set each of the other WLs, including a neighbor WL neighboring to the target WL, to a predefined full conducting voltage or to a predefined partial conducting voltage lower than the full conducting voltage, pre-charge the BLs, and while discharging the BLs, read a page from a group of target memory cells multiple times, to produce multiple respective binary readouts, at least one of the readouts corresponds to setting the neighbor WL to the partial conducting voltage, apply the combinational logic to the readouts to produce (i) output bits of the page, and (ii) confidence levels associated with the output bits, and transmit the output bits and the confidence levels to a controller.
What exactly they claim (claim 1)
1. An apparatus, comprising: a sampler configured to be connected to a plurality of memory cells coupled to multiple Word Lines (WLs) and to multiple Bit Lines (BLs), the sampler further configured to; set a first read voltage to a target WL among the multiple WLs, and set each of the WLs other than the target WL, including a neighbor WL neighboring to the target WL, to a predefined full conducting voltage or to a predefined partial conducting voltage lower than the full conducting voltage; pre-charge the multiple BLs; and while discharging the pre-charged BLs, read a page from a group of target memory cells that are coupled to the target WL, multiple times, to produce multiple respective binary readouts, wherein at least one of the binary readouts corresponds to setting the neighbor WL to the partial conducting voltage; and combinational logic implemented in hardware and configured to: produce, based on the binary readouts, (i) output bits of the page, and (ii) respective binary confidence levels associated with the output bits; and transmit the output bits and the binary confidence levels to a controller.
Facts
- Company
- Apple (Apple Inc.)
- Official title
- Low latency crosstalk mitigation in a nonvolatile memory
- Publication number
- US20260319884A1
- Application number
- 19542687
- Filed
- Feb 18, 2026
- Published
- Oct 15, 2026
- Inventors
- 4
- Claims
- 18
Classified under
G06F 11/1016 Physics & computingG06F 11/1004 Physics & computingMore from Apple in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.