Apple patents chip power saving that adjusts based on workload
Apple describes a processor design where a power management circuit monitors how hard the chip is working. When the workload drops below a certain level, the system switches to a lower power state and uses clock gating to stop sending signals to idle parts of the chip. The specific power-saving method used depends on the timing margin available in that lower power state.
In the filing’s own words
A processor circuit having performance state-aware clock-gating is disclosed. A processor circuit includes a plurality of circuit blocks and a power management circuit. The power management circuit determines a workload demand for the circuit blocks. In response to a determination that the workload demand is less than a threshold level, the power management circuit changes a performance state from a first performance state to a second performance state that consumes less power. The power management circuit further, in the second performance states, activates a first operational mode (e.g., that performs clock-gating of various circuits) based on a timing margin associated with the second performance state.
What exactly they claim (claim 1)
1. An apparatus, a processor circuit including a plurality of circuit blocks; and a power management circuit configured to: determine a workload demand for one or more of the plurality of circuit blocks; and in response to a determination that the workload demand is less than a threshold level: change a performance state of the processor circuit from a first performance state of a plurality of performance states to a second performance state of the plurality of performance states, wherein an amount of power consumed by the processor circuit operating in the second performance state is less than the amount of power consumed by the processor circuit operating in the first performance state; and activate a first operational mode in at least one circuit block of the plurality of circuit blocks, wherein the first operational mode is based on a timing margin associated with the second performance state.
Facts
- Company
- Apple (Apple Inc.)
- Official title
- PERFORMANCE STATE AWARE DYNAMIC CLOCK GATING
- Publication number
- US20260299666A1
- Application number
- 19089363
- Filed
- Mar 25, 2025
- Published
- Oct 1, 2026
- Inventors
- 5
- Claims
- 20
Classified under
G06F 1/324 Physics & computingG06F 1/3228 Physics & computingMore from Apple in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.