Apple patents memory trick to stop wasted write time
Apple describes a method for memory controllers to monitor how efficiently data is being written to memory banks. If the system detects too much idle time during a write operation, it stops the current task early and gives the remaining time slots to a different write request.
In the filing’s own words
Write bandwidth efficiency recovery for memory subsystems is disclosed. A memory controller is configured to perform read and write transactions with a memory having a plurality of banks. Write transactions are performed in an allocated number of write slots, each of which includes a write of data to a given bank, with a complete write comprising writing to the banks in a sequence. The memory controller is configured to determine a bandwidth efficiency in response to completing writing the data based on an amount of idle time until a first memory bank to which data was written is accessible again and to terminate the write transaction in response to a determination that the bandwidth efficiency is less than a threshold value, allocating any unused write slots for the first write transaction to a second write transaction to the first memory in response to a termination of the first write transaction.
What exactly they claim (claim 1)
1. An apparatus comprising: a first memory having a first plurality of memory banks; and a memory controller circuit coupled to the first memory by at least one data bus and at least one command bus, wherein the memory controller circuit is configured to perform transactions with the first memory, the transactions including read transactions and write transactions, wherein a first write transaction is to be allocated a number of write slots, wherein a given write slot comprises a period of time to write data to one of the first plurality of memory banks, and wherein the first write transaction comprises writing data to ones of the first plurality of memory banks beginning with a first memory bank of the first plurality of memory banks, wherein the memory controller circuit is further configured to: determine a bandwidth efficiency in response to completing write of the data to the first plurality of memory banks, wherein the bandwidth efficiency is based on an amount of idle time until the first memory bank is accessible again; terminate the first write transaction in response to a determination that the bandwidth efficiency is less than a threshold value; and allocate any unused write slots for the first write transaction to a second write transaction to the first memory in response to a termination of the first write transaction.
Facts
- Company
- Apple (Apple Inc.)
- Official title
- WRITE BANDWIDTH EFFICIENCY RECOVERY
- Publication number
- US20260277443A1
- Application number
- 19078587
- Filed
- Mar 13, 2025
- Published
- Sep 17, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G06F 3/0613 Physics & computingG06F 3/0659 Physics & computingG06F 3/0679 Physics & computingMore from Apple in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.