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ApplePatent applicationChips & hardwareInterest 2/10

Apple patents circuit that fixes clock signal timing errors

Apple describes a hardware circuit that adjusts the timing of a clock signal, which acts as the heartbeat for computer chips. It measures the length of the signal's high and low phases and tweaks the timing of the edges to keep them balanced.

Why it mattersThis is a routine improvement to internal chip design that helps ensure digital circuits operate reliably by correcting minor timing inconsistencies.

In the filing’s own words

A duty cycle correction circuit is disclosed. The duty cycle correction circuit includes a delay circuit configured to receive an input clock signal, a first control signal, and a second control signal and control, based on the input clock signal, the first control signal, and the second control signal, respective delays of a rising edge and a falling edge of an output clock signal. The duty cycle correction circuit is configured to adjust a duty cycle of the output clock signal on a cycle-by-cycle basis. The duty cycle correction circuit also includes a time-domain converter circuit configured to generate a comparison signal based on respective durations of a high phase and a low phase of the output clock signal and a decoder circuit configured to generate the first and second control signals using the comparison signal.

What exactly they claim (claim 1)

1. An apparatus, comprising: a duty cycle correction circuit that includes: a delay circuit configured to: receive an input clock signal, a first control signal, and a second control signal; control, based on the input clock signal, the first control signal, and the second control signal, respective delays of a rising edge and a falling edge of an output clock signal; and adjust a duty cycle of the output clock signal on a cycle-by-cycle basis; a time-domain converter circuit configured to generate a comparison signal based on a duration of a first phase of the output clock signal; and a decoder circuit configured to generate the first and second control signals using the comparison signal.

Facts

Company
Apple (Apple Inc.)
Official title
DYNAMIC DUTY CYCLE MONITOR AND CORRECTION CIRCUIT
Publication number
US20260269817A1
Application number
19074886
Filed
Mar 10, 2025
Published
Sep 10, 2026
Inventors
3
Claims
20

Classified under

H03K 5/1565 Electricity & electronicsH03K 5/134 Electricity & electronicsH03K 2005/00195 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.