Apple patents memory timing trick to recover lost data bandwidth
Apple describes a method for a memory controller to track unused time slots while writing data to a chip's memory. If some write slots are left empty, the controller adds that extra time to the next read operation to ensure the memory bus stays fully utilized.
In the filing’s own words
A memory subsystem with timing compensation for bandwidth recovery is disclosed. The memory subsystem includes a memory having and a memory controller coupled thereto via a memory bus. The memory controller is configured perform a write transaction that includes writing data to the memory circuit during ones of a plurality of write slots and determine, while performing the write transaction and based on an operating frequency of the memory bus, a number of idle write slots of the plurality of write slot during which data is not written to the memory. The memory controller is further configured to add a number of read slots corresponding to the number of idle write slots to a total number of read slots for a read transaction, and perform, upon completing the write transaction, a read transaction that includes reading data from the memory circuit during the total number of read slots.
What exactly they claim (claim 1)
1. An apparatus, comprising: a memory circuit including a plurality of memory banks; and a memory controller circuit coupled to the memory circuit via a memory bus, wherein the memory controller circuit is configured to: perform a write transaction that includes writing data to the memory circuit during corresponding ones of a plurality of write slots; determine, while performing the write transaction and based on an operating frequency of the memory bus, a number of idle write slots, of the plurality of write slots, during which data is not written to the memory circuit; increment, by a number of read slots corresponding to the number of idle write slots, a total number of read slots for a read transaction; and perform, in response to a determination that the write transaction has completed, a read transaction that includes reading data from the memory circuit during the total number of read slots.
Facts
- Company
- Apple (Apple Inc.)
- Official title
- Memory transaction timing compensation
- Patent number
- US12769451B2
- Application number
- 19078650
- Filed
- Mar 13, 2025
- Granted
- Oct 20, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G06F 3/0613 Physics & computingG06F 3/0659 Physics & computingG06F 3/0673 Physics & computingMore from Apple in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.