Apple patents chip design that keeps math results ready for next steps

1. A neural processor circuit, comprising: a plurality of neural engine circuits comprising a first neural engine circuit and a second neural engine circuit, at least one of the plurality of neural engine circuits configured to perform a convolution operation to generate output data; a planar engine circuit that is separated from and coupled to the plurality of neural engine circuits including the first neural engine circuit and the second neural engine circuit, the planar engine circuit including: a first filter circuit configured to perform a reduction operation to reduce a patch tensor of a first rank to another tensor of a second rank lower than the first rank by removing one or more dimensions of the patch tensor of the first rank for each patch of a plurality of patches of a tensor for a dataset of an input data originating from the output data to generate a respective reduced value of a plurality of reduced values, the respective reduced value associated with a corresponding channel of a plurality of channels of the tensor for the dataset, the respective reduced value being generated based on values of elementwise operations between a first work unit of each patch and a second work unit of another patch, wherein the tensor of the input data comprises more than 3 dimensions and the plurality of patches, at least one patch of the plurality of patches includes 3 dimensions and a plurality of work units, and at least one work unit of the plurality of work units represents the dataset of a size capable of being processed by the planar engine circuit in a single operating cycle; a second filter circuit coupled to the first filter circuit, the second filter circuit configured to: receive a first tensor and a second tensor as part of the output data; and perform an elementwise operation between the first tensor and the second tensor to generate the tensor for the first filter circuit; and a line buffer coupled to the first filter circuit, the line buffer configured to: store the plurality of reduced values for the plurality of channels being transferred from one or more registers within the first filter circuit, and retain the plurality of reduced values for a defined number of operating cycles as indicated by a refresh flag stored in another register external to the first filter circuit and defining resetting of the line buffer; and a data processor circuit coupled to the planar engine circuit and the plurality of neural engine circuits, the data processor circuit configured to: store the output data obtained from at least one neural engine circuit; and send the output data to the planar engine circuit, the output data comprising the dataset as the input data for the plurality of patches and the plurality of channels of the tensor.