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GoogleGranted patentSecurity & privacyInterest 6/10

Google patents memory system that scrambles data paths to block malware

This patent describes a computer memory system that randomly swaps the physical wires connecting the processor to memory during a restart. By changing which wire carries which piece of data, the system alters the physical layout of memory locations. This makes it difficult for malicious software to find and exploit specific memory addresses after the computer restarts.

Why it mattersIt offers a hardware-level defense against malware that tries to hide in specific memory spots, adding an extra layer of protection for devices like servers or phones.

In the filing’s own words

This document describes technology for a runtime memory system that utilizes unpredictable multiplexing of memory bus lines. The technology dynamically reassigns data and/or address bus connections between a processor and its runtime memory during warm reset operations. The bus line assignments are made through a multiplexing mechanism—for example, data bus line 01 from the processor may be reassigned to link with bus line 23 at the runtime memory system interface. When a warm reset occurs, the physical mapping of memory locations changes due to this bus line reassignment. The system maintains standard memory operations while implementing this dynamic bus line configuration. Malicious software relying upon memory-resident exploit becomes inoperable after warm reset due to the changed physical memory topology created by the bus line reassignment process.

What exactly they claim (claim 1)

1. An apparatus comprising: a processor; a runtime memory system; and a bus system including: one or more buses, each bus having multiple lines coupling the processor and the runtime memory system together, wherein the one or more busses are configured to facilitate reading and/or writing data from/to the runtime memory by the processor; a mux configured to selectively link each of multiple processor-mux lines to one of multiple mux-memory lines; and a bus driver configured to control selective linkage of each of the multiple processor-mux lines to one of the multiple mux-memory lines.

Facts

Company
Google (Google LLC)
Official title
Runtime memory system with unpredictably assigned multiplexed memory bus lines
Patent number
US12762071B2
Application number
19070782
Filed
Mar 5, 2025
Granted
Oct 13, 2026
Inventors
1
Claims
10

Classified under

G06F 13/16 Physics & computingG06F 2213/40 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.