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AppleGranted patentChips & hardwareInterest 4/10

Apple patents chip design that doubles data speed and eases testing

Apple has been granted a patent for a specific circuit design used inside computer chips to move data faster. The design uses a component called a flip-flop that captures data on both the rising and falling edges of a clock signal, effectively doubling the data flow rate. It also includes a special 'shadow' latch that allows engineers to test the circuit without disrupting normal operations.

Why it mattersThis is a low-level hardware improvement that helps make internal data transfers more efficient and easier to verify during manufacturing, though it does not directly change how users interact with their devices.

In the filing’s own words

A double-pumped communications channel utilizing a double-edge-triggered flip-flop is disclosed. The double-edge-triggered flip-flop includes first and second latches configured to latch first and second bits, respectively, on respective ones of rising and falling edges of a clock signal. A shadow latch is coupled to an output of one of the first or second latches and is configured to, during a test mode, a third bit from the coupled one of the first or second latches. During an operational mode, the flip-flop circuit is configured to relay data, via a first output, on alternating edges of the clock signal. During a test mode, the flip-flop circuit is configured to relay test data on a clock edge opposite of the one to which the coupled one of the first or second latches is responsive. A plurality of double-edge-triggered flip-flop circuits may be coupled in series to form a communications channel.

What exactly they claim (claim 1)

1. An apparatus, comprising: a communications channel comprising a plurality of flip-flop circuits coupled in series, wherein ones of the plurality of flip-flop circuit are configured to sample data in response to a rising edge and a falling edge of a clock signal, wherein plurality of flip-flop circuits includes a first flip-flop circuit, wherein the first flip-flop circuit includes: a first latch configured to receive a first bit in response to the rising edge of the clock signal; a second latch configured to receive a second bit in response to the falling edge of the clock signal; and at least one shadow latch coupled to an output of one of the first latch or the second latch, wherein the shadow latch is configured to receive a third bit from an output of the one of the first latch and the second latch; wherein, the first flip-flop circuit is configured, during an operational mode, to relay data, via a first output, from the first latch and the second latch on alternating edges of the clock signal; and wherein, the first flip-flop circuit is configured, during a test mode, to relay test data from the shadow latch on an edge of the clock signal opposite that of the one of the first latch or the second latch to which the shadow latch is coupled.

Facts

Company
Apple (Apple Inc.)
Official title
Double-pumped communication channel using double edge-triggered flip-flop with scan functionality
Patent number
US12744524B1
Application number
19082499
Filed
Mar 18, 2025
Granted
Sep 22, 2026
Inventors
7
Claims
20

Classified under

H03K 17/51 Electricity & electronicsH03K 3/037 Electricity & electronicsH03K 19/20 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.