Apple patents smarter way to split graphics tasks across chip parts

1. An apparatus, comprising: graphics control circuitry configured to implement a plurality of logical slots; a first graphics processor sub-unit that is configured to implement at least a first distributed hardware slot and a second graphics processor sub-unit that is configured to implement at least a second distributed hardware slot; and control circuitry configured to: determine a target number of distributed hardware slots to be utilized for a set of graphics work, based on control information for the set of graphics work; and assign respective portions of the set of graphics work, from a logical slot of the plurality of logical slots, to at least the first and second distributed hardware slots for execution, including to; assign a first proper sub-set that includes a first portion of the set of graphics work to the first distributed hardware slot, in response to a determination that the target number is greater than a number of available distributed hardware slots but that the first distributed hardware slot is available; assign a second proper sub-set that includes at least a second portion of the set of graphics work to the second distributed hardware slot, in response to a determination that the second distributed hardware slot has become available, wherein the assignment of the first proper sub-set is prior to assignment of the second proper sub-set; wherein the assignment of the first proper sub-set includes to store the first portion of the set of graphics work in work queue circuitry for the first distributed hardware slot and includes to program configuration registers for the first distributed hardware slot, to support execution of the first portion of the set of graphics work by first shader circuitry of the first graphics processor sub-unit; and wherein the assignment of the second proper sub-set includes to store the second portion of the set of graphics work in work queue circuitry for the second distributed hardware slot and includes to program configuration registers for the second distributed hardware slot, to support execution of the second portion of the set of graphics work by second shader circuitry of the second graphics processor sub-unit.