Apple patents memory system that pauses writes for urgent reads
Apple has been granted a patent for a computer memory system that can interrupt a batch of data writes to handle an urgent read request. The processor tags specific reads as critical, and if the system has enough space to save the paused writes, it switches to processing the urgent read immediately.
In the filing’s own words
In an embodiment, a computer system includes a memory system configured to couple to one or more memory devices and processor circuitry configured to issue read and write requests to the memory system. The memory system is configured to receive, during a write turn in which a plurality of write requests are processed, a read request and an indication of a criticality of the read request assigned by the processor circuitry. The memory system is further configured to, based on the indication identifying that the read request is a critical read request and a detection that a set of activation criteria is satisfied, transition, to process the critical read request, from the write turn to a read turn without completing the write turn. The memory system is configured to perform the read turn in which a plurality of read requests are processed including the critical read request.
What exactly they claim (claim 1)
1. An apparatus, comprising: a memory system configured to couple to one or more memory devices, wherein the memory system includes a set of write queues configured to store write requests; processor circuitry configured to issue read and write requests to the memory system; and wherein the memory system is configured to: receive, during a write turn in which a plurality of write requests are processed, a read request and an indication of a criticality of the read request assigned by the processor circuitry; and based on the indication identifying that the read request is a critical read request and a detection that a set of activation criteria is satisfied, transition, to process the critical read request, from the write turn to a read turn without completing the write turn, wherein the set of activation criteria includes a criterion that there is at least a threshold number of available entries in the set of write queues to store write requests having a first particular prioritization level.
Facts
- Company
- Apple (Apple Inc.)
- Official title
- Mechanisms for processing memory requests based on criticality
- Patent number
- US12730763B2
- Application number
- 18978516
- Filed
- Dec 12, 2024
- Granted
- Sep 8, 2026
- Inventors
- 6
- Claims
- 17
Classified under
G06F 13/1626 Physics & computingG06F 12/1045 Physics & computingG06F 13/1642 Physics & computingMore from Apple in Chips & hardware
- Apple patents glass chip base that uses light to move data Oct 8, 2026
- Apple patents radar that maps rooms using moving objects Sep 1, 2026
- Apple patents display method that reuses static images to save power Sep 1, 2026
- Apple patents stretchable OLED displays with sealed pixel islands Sep 8, 2026
- Apple patents method to fix color fringes in high-resolution displays Sep 8, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.